1. Field of the Invention
The invention relates to a method for fabricating strained-silicon transistors.
2. Description of the Prior Art
The performance of MOS transistors has increased year after year with the diminution of critical dimensions and the advance of large-scale integrated circuits (LSI). However, it has been recently pointed out that the miniaturization attained by a lithographic technology has reached its limit. Therefore, how to improve the carrier mobility so as to increase the speed performance of MOS transistors has become a major topic for study in the semiconductor field. For the known arts, attempts have been made to use a strained silicon layer, which has been grown epitaxially on a silicon substrate with a silicon germanium (SiGe) layer disposed therebetween. In this type of MOS transistor, a biaxial tensile strain occurs in the epitaxy silicon layer due to the silicon germanium which has a larger lattice constant than silicon, and, as a result, the band structure alters, and the carrier mobility increases. This enhances the speed performance of the MOS transistors.
Please refer to FIGS. 1-4. FIGS. 1-4 illustrate a method of utilizing selective epitaxial growth process for fabricating a strained-silicon transistor according to the prior art. As shown in FIG. 1, a semiconductor substrate 10, such as a silicon substrate is provided. The semiconductor substrate 10 includes a gate structure 12 thereon, in which the gate structure 12 includes a gate dielectric 14 and a gate 16 disposed on the gate dielectric 14. An ion implantation process is performed thereafter to inject a p-type or n-type dopant of smaller concentration into the semiconductor substrate 10. The implantation process preferably forms a lightly doped drain 24 in the semiconductor substrate 10 surrounding the gate structure 12. An offset spacer 18 is formed on the sidewall of the gate structure 12 and a spacer 20 is formed surrounding the offset spacer 18 thereafter. Preferably, the gate dielectric 14 is composed of silicon dioxide, the gate 16 is composed of doped polysilicon, and the offset spacer 18 and the spacer 20 are composed of oxides and nitride-oxides respectively. The active area of the semiconductor substrate 10 including the gate structure 12 is preferably encompassed by a shallow trench isolation 22.
As shown in FIG. 2, another ion implantation process is performed to inject a p-type or n-type dopant of higher concentration into the semiconductor substrate 10 surrounding the lightly doped drain 24. This ion implantation process forms a source/drain region 26 and completes the fabrication of a PMOS transistor or an NMOS transistor. Thereafter, a rapid thermal annealing process is performed by using a temperature between 900 degrees to 1000 degrees to activate the dopants injected into the semiconductor substrate 10 and repair the lattice structure of the substrate damaged during the ion implantation process.
As shown in FIG. 3, an etching process is conducted by using the gate structure 12, the offset spacer 18, and the spacer 20 as a mask to form a recess atop the gate 16 and in the source/drain region 26. Next, a baking process is performed by using a temperature between 700 degrees to 950 degrees to remove the remaining oxides from the surface of the recess 28 and repair the surface roughness of the recess.
After the baking process is conducted, as shown in FIG. 4, a selective epitaxial growth process is performed to form an epitaxial layer 30 composed of silicon germanium or silicon carbide in the recess 28, thereby completing the fabrication of a strained-silicon transistor. Specifically, materials used for forming the epitaxial layer can be selected according to the nature of the transistor. For instance, if the fabricated transistor is a PMOS transistor, the epitaxial layer can be composed of silicon germanium. On the other hand, if the fabricated transistor is an NMOS transistor, the epitaxial layer can be composed of silicon carbide.
It should be noted that the aforementioned fabrication process typically includes following drawbacks. First, an etching process is commonly conducted to form a recess in the source/drain region of the substrate after the formation of the epitaxial layer, as shown in FIG. 3. This step provides a growing surface for the epitaxial layer but also causes the dopants within the source/drain region to be gathered in the edge region of the recess, thereby inducing an uneven distribution of dopants and affecting the performance of the MOS transistor.
Secondly, after the formation of the source/drain region, a rapid thermal annealing process is conducted to activate the injected dopants by diffusing the dopants throughout the source/drain region. Under normal condition, the activated dopants should have perfect bonding. However, the baking process performed before the formation of the epitaxial layer typically utilizes a temperature lower than the rapid thermal annealing process to remove the remaining oxides from the surface of the recess and repair the surface roughness of the recess. Despite the fact that the baking process provides an ideal growing surface for the epitaxial layer, this lowered temperature carried by the baking process would disrupt the bonding of the dopants, which ultimately increases the overall resistance and induces a deactivation phenomenon.
Please refer to FIG. 5 and FIG. 6. FIG. 5 illustrates the operating current (Ion) and current leakage (Ioff) of a PMOS transistor under different baking temperatures whereas FIG. 6 illustrates the resistance of the PMOS transistor under different baking temperatures. As shown in FIG. 5, as the temperature of the baking process increases, the operating current of the PMOS transistor degrades accordingly. For instance, under the same leaking current, if a device being performed without any baking process were taken as a reference point, a device being performed with a baking process at 750 degrees would demonstrate a current degradation of approximately 7%, and a device being performed with a baking process at 850 degrees would demonstrate a current degradation of approximately 13.6%. Since the resistance of a device increases as the operating current decreases if the voltage remains unchanged, the resistance of the device would also increase accordingly as the temperature of the baking process increases. As shown in FIG. 6, as the temperature of the baking process increases up to approximately 850 degrees, the resistance of the PMOS transistor also reaches a maximum point. As discussed previously, an increase in resistance would result in a deactivation phenomenon and damage the bonds within the dopants. Due to the importance of the baking process in the current process for fabricating the epitaxial layer, how to improve the problem of deactivation caused after the baking process has become a critical task.